1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors having strained channel regions by using stress memorization techniques so as to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced to fabricate integrated circuits, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface that is defined by highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode located close to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant profile, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region is a dominant factor that determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is an important design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For instance, the thickness of the gate insulation layer, typically an oxide-based dielectric, has to be reduced with reducing the gate length, wherein a reduced thickness may result in increased leakage currents, thereby posing limitations for oxide-based gate insulation layers at approximately 1-2 nm. Thus, the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, for example, for compensating for short channel effects with oxide-based gate dielectric scaling being pushed to the limits with respect to tolerable leakage currents. It has, therefore, been proposed to replace silicon dioxide-based dielectrics, at least partially, with so-called high-k dielectric materials having a dielectric constant of 10.0 or higher. Also, the channel conductivity of the transistor elements may be enhanced by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a significant performance improvement.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region along the channel length direction for a standard crystallographic orientation increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity. On the other hand, uniaxial compressive strain in the channel region for the same configuration may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach, since, for example, strained silicon may be considered as a new type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
In some approaches, external stress created by, for instance, permanent overlaying layers, spacer elements and the like is used in an attempt to create a desired strain within the channel region. Although a promising approach, the process of creating the strain in the channel region by applying a specified external stress may depend on the efficiency of the stress transfer mechanism for the external stress provided by, for instance, contact layers, spacers and the like into the channel region to create the desired strain therein. Thus, for different transistor types, differently stressed overlayers have to be provided, which may result in a plurality of additional process steps, wherein, in particular, any additional lithography steps may significantly contribute to the overall production costs. Moreover, the amount of stress-inducing material and in particular the intrinsic stress thereof may not be arbitrarily increased without requiring significant design alterations.
Furthermore, upon further scaling the transistor dimensions, the lateral offset between adjacent gate electrode structures of transistors is also reduced, thereby significantly restricting the possibility of depositing highly stressed dielectric materials above the closely spaced transistor elements. Consequently, due to the significant restrictions of any such external strain-inducing mechanisms in sophisticated semiconductor devices, increasingly, internal strain-inducing sources, such as an embedded strained semiconductor alloy, such as silicon/germanium and the like, may be incorporated into the drain and source areas in order to provide a high uniaxial strain component in the adjacent channel region. The well-established silicon/germanium material may be provided in P-channel transistors in order to obtain a high compressive strain, while, on the other hand, tensile strain semiconductor alloys, such as silicon/carbon, may not provide comparable high strain levels due to manufacturing-related issues in providing efficient silicon/carbon material compositions.
In other promising approaches, a substantially amorphized region may be formed in the active region of the transistors laterally adjacent to the gate electrode at an appropriate intermediate manufacturing stage, wherein the amorphized region is then re-crystallized in the presence of a rigid layer formed above the transistor area. For this purpose, silicon nitride material has proven to be a very viable material for the rigid layer since, without intending to restrict the present application to the following explanation, silicon nitride may be provided as a very dense and stiff material, which may thus efficiently force the underlying substantially amorphized semiconductor material to regrow in a highly strained state upon annealing the semiconductor device. That is, during the anneal process for re-crystallizing, the growth of the crystal will occur under stress conditions created by the rigid overlayer, for instance caused by shrinkage of the previously amorphized volume, thereby obtaining a highly tensile strained crystal state. After the re-crystallization, the stress-inducing layer may be partly or completely removed, wherein, nevertheless, a certain amount of strain may be conserved in the re-grown lattice portion. This effect is referred to hereinafter as stress memorization.
Although stress memorization techniques, possibly in combination with efficient silicon/germanium-based strain-inducing mechanisms for P-channel transistors, represent a promising approach for enhancing performance upon further scaling the overall dimensions of transistor elements, other negative influences may have an increasing effect on the overall performance of the transistors. For example, the parasitic capacitance in sophisticated transistors, for instance caused by PN junctions and the like, increasingly contribute to the overall transistor behavior. Similarly, due to the reduced dimensions, the parasitic capacitance of the interconnect elements for providing signals and supply voltages to the highly scaled transistors may increasingly reduce overall performance of the transistors. For example, the fringing capacitance of the gate electrode, i.e., the parasitic capacitance generated between any contact elements and the gate electrode of the transistors, may increasingly contribute to an inferior high frequency behavior of the transistors, wherein the overall dielectric constant of the dielectric material enclosing the gate electrode structure may be one of the dominant contributors to an increased parasitic capacitance. In particular, in efficient stress memorization techniques, the silicon nitride material used for re-crystallizing the amorphized areas in the active region in a tensile strained state may additionally be used as a spacer element after patterning the corresponding silicon nitride overlayer after performing the anneal process. Although using the strain-inducing silicon nitride layer as a spacer material provides a very efficient overall process flow, the presence of the silicon nitride material in the form of a sidewall spacer element at the gate electrode structures may cause an increased parasitic capacitance due to the moderately high-k value of silicon nitride material. On the other hand, the removal of the silicon nitride layer after generating the desired tensile strain component may result in undue process complexity.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.